The invention relates generally to memory interface circuitry, and more particularly to extendible timing circuitry for double data rate memory applications.
Memory interface circuitry generally may include arbitration circuitry, application specific circuitry, and physical layer interface circuitry. This circuitry is generally provided by an asynchronous integrated circuit (ASIC) separate from the memory. The arbitration circuitry generally performs functions relating to accessing a system bus using an implementation specific bus protocol and otherwise formats transmitted and received data and instructions as appropriate. The application specific circuitry generally includes control circuitry for generating memory access commands and circuitry for generally controlling interaction with a memory. The physical (PHY) circuitry transmits signals from the ASIC to the memory and receives signals from the memory.
Design of PHY circuitry for interfacing with double data rate (DDR) memories, for example, may be difficult. A DDR memory generally transfers data on both a high clock transition and a low clock transition, thereby providing effectively a doubling of the effective clock rate. Accordingly, PHY circuitry interfacing with a DDR memory must also generally be able to process data at effectively double the clock rate of other circuitry. In addition, a DDR memory also requires use of a bidirectional data strobe signal (DQS), the timing of which may be 90 degrees out of phase with the clock signal during read operations and edge aligned during write operations, and a DDR memory also generally imposes tight timing restrictions on signals provided to and from the memory.
Furthermore, clock and signal timing may be adversely affected by a number of factors. For example, timing of clock signals provided to a port of the ASIC may be skewed by routing dependent propagation delay, both as to length of signal routing, variations in capacitance and inductance of signal paths, cross-talk or other noise from signals on nearby signal paths. Clock generation or reproduction circuitry may also be adversely impacted by power supply voltage variations and power supply related noise, particularly when used with circuitry using high switching frequencies. Clock and timing may also be unduly affected by provision of multiple power supply domains, which may be required for analog circuits and digital circuits, by voltage gradients within or across power supply domains, particularly larger size domains, and at transitions across power supply domains.
Moreover, resolution of timing related issues, whether it is distortion of a data eye or clock skew, may be difficult. Ensuring that a circuit design meets appropriate timing budgets may often be a time consuming process, often requiring the use of skilled personnel and complicated analysis for every design. Further, often when a circuit design does meet the appropriate timing budget and other constraints, the design is only valid for the particular circuit, and the circuit cannot be extended for use with additional memories without re-design and concomitant time consuming time budget revivification.